Articles about 'EUVL'

Winter Issue 2017

21 December, 2017


"EUV Is Coming"

After many years of hearing that EUV is almost ready for prime time, the tide is finally coming in. A decade of slow but steady progress has resulted in exposure tools that can expose on the order of 1,000 wafers a day on a regular basis. This may be shy of the requirements for high volume manufacturing (HVM), but it is certainly more than enough to support solid development programs and pilot line production. Almost all leading edge manufacturers have announced plans for early introduction in the 2018-19 timeframe, with HVM to follow within 1-2 years if the economics and technology are proven to be viable. Papers at the SPIE Photomask Technology (BACUS) + EUV Lithography conference in Monterey, SPIE Advanced Lithography 2017 conference and Photomask Japan 2017 symposium all highlighted the emerging maturity of EUV tools and processes, as well as the remaining challenges. It is certainly an exciting time for the EUV community, and a time of impending change for the mask making world.

November 2 2017 Issue

2 November, 2017


Hotspot Management: Process Window Discovery and Control

With advanced patterning techniques and shrinking design nodes come the proliferation of hotspots, and complex correlations between hotspots and increasingly narrow process margins. Additionally we see a change in the causes of hotspots; design systematics related to layout or OPC no longer dominate as the primary source of hotspots. We are seeing an increasing effect from process systematics, which are related to design but are induced by process related sources (wafer non-uniformity, process variations), or, in case of multi-patterning schemes, also by interactions between the different masks. These hotspot complexities are driving the need for process window discovery, expansion and control.

July Issue 2017

1 July, 2017


Patterning Trends for Advanced IC Manufacturing

With the move to sub-10nm design nodes, the utilization of multi-patterning techniques has intensified, with triple patterning (LELELE), self-aligned quadruple patterning (SAQP), and other complex patterning technologies being utilized to achieve smaller design nodes. IC manufacturers face many technical challenges when implementing advanced multi-patterning, including: the proliferation of process and design systematic defects; extremely tight patterning specifications; and, the erosion of process margins. In this environment, it has become necessary for IC manufacturers to: (1) utilize comprehensive strategies to find and control process and patterning variations at the source.

Spring Issue 2016

19 May, 2016

Advanced Overlay: Sampling and Modeling for Optimized Run-to-Run Control

In recent years overlay control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, new challenges must be addressed for effective run-to-run overlay control. Two of these challenges are addressed in this study by new advanced analysis techniques: (1) sampling optimization for run-to-run control; and (2) bias-variance tradeoff in modeling. The sampling and modeling solutions proposed are validated by APC simulations to estimate run-to-run performance, lot-to-lot and wafer-to-wafer model term monitoring to estimate stability, and ultimately high volume manufacturing tests to monitor on-product overlay by densely measured overlay data.

Winter Issue 2014

9 January, 2014

PRODUCT SPOTLIGHT: Broadband Plasma Defect Inspection

Advanced defect detection, metrology, and review systems are utilized by IC manufacturers to ramp new processes, increase yield and ultimately increase profitability. KLA’s unique broadband plasma inspectors offer the most capable technology for discovering all of the yield-critical defect types on leading-edge devices.

Summer Issue 2012

12 June, 2012

Introducing the Surfscan SP3 450

The Surfscan® SP3 450 is the first of KLA’s process control systems capable of handling and inspecting 450mm wafers. As a new configuration of the market-leading Surfscan SP3 platform, these fully-automated unpatterned wafer inspection systems feature unique deep ultra-violet (DUV) sensitivity and unique high-resolution SURFmonitorTM surface quality characterization to support sub-20nm node requirements. The Surfscan SP3 450 enables manufacturing process control for 450mm polished silicon and epitaxial silicon substrates and also delivers critical capability for manufacturers of 450mm process equipment, such as wet clean tools, CMP pads, slurries and polishers, film deposition tools and annealing systems.

Summer Issue 2011

12 July, 2011

SPOTLIGHT: 2011 Lithography Users’ Forum Keynote Presentation

Coinciding with the 2011 SPIE Advanced Lithography exhibition, KLA hosted its one-of-a-kind Lithography Users' Forum (LUF). Annually, this event brings together the industry’s leading lithographers for networking, information sharing, and discussions surrounding challenges facing the industry and possible solutions.

Spring Issue 2010

28 April, 2010

SPOTLIGHT: 2010 Lithography Users' Forum

Over 300 technologists, scientists and engineers gathered in San Jose, California on February 21st to attend KLA’s 11th Annual Lithography Users’ Forum. This annual event serves as a sneak peek at more than 20 technical papers co-authored by KLA engineers and customers presented at SPIE’s Advanced Lithography conference. The forum covered current metrology and inspection challenges associated with today’s advanced lithography processes, and KLA’s solutions to those challenges. The event highlight was the keynote, “EUV, EBDW—ArF Replacement or Extension?” presented by Yan Borodovsky, director of the Advanced Lithography Technology, Manufacturing Group at Intel Corp.

Spring Issue 2007

2 April, 2007

Spring 2007 Volume 9, Issue 1

Preview the interactive digital publishing of YMS Magazine to simulate the experience of reading a print publication online.

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