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Articles about 'Pattern Wafer Geometry'

Spring Issue 2016

19 May, 2016

Advanced Overlay: Sampling and Modeling for Optimized Run-to-Run Control

In recent years overlay control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, new challenges must be addressed for effective run-to-run overlay control. Two of these challenges are addressed in this study by new advanced analysis techniques: (1) sampling optimization for run-to-run control; and (2) bias-variance tradeoff in modeling. The sampling and modeling solutions proposed are validated by APC simulations to estimate run-to-run performance, lot-to-lot and wafer-to-wafer model term monitoring to estimate stability, and ultimately high volume manufacturing tests to monitor on-product overlay by densely measured overlay data.

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