Process Watch is a monthly column in Solid State Technology, also appearing in translation in SST China and SST Taiwan.




Process Watch: Salami Slicing Your Yield


In a previous Process Watch article [1], we showed that big excursions are usually easy to detect but finding small excursions requires a combination of high capture rate and low noise. We also made the point that, in our experience, it’s usually the smaller excursions which end up costing the fab more in lost product. Catastrophic excursions have a large initial impact but are almost always detected quickly. By contrast, smaller “micro-excursions” sometimes last for weeks, exposing hundreds or thousands of lots to suppressed yield.

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Reducing Production Costs with Process Control


Instrumental to having an efficient, low-cost fab is the ability to collect meaningful information about the process in a timely fashion. Process control tools (metrology and inspection) are the eyes and ears of the fab in that they provide insight into what’s working and what’s not: they are an investment in “process information.” In a 2007 paper2 the National Institute of Standards and Technology (NIST) estimated that the average return on investment for metrology alone was 300 percent.

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Reducing Production Costs with Process Control


Instrumental to having an efficient, low-cost fab is the ability to collect meaningful information about the process in a timely fashion. Process control tools (metrology and inspection) are the eyes and ears of the fab in that they provide insight into what’s working and what’s not: they are an investment in “process information.” In a 2007 paper2 the National Institute of Standards and Technology (NIST) estimated that the average return on investment for metrology alone was 300 percent.

Read More >>
Simplified Chinese Translation >>
Traditional Chinese Translation >>


Process Steps and the Tyranny of Numbers


Anything that degrades the quality of the measurement also degrades the quality of the process because it introduces more variability into the Statistical Process Control (SPC) charts which are windows into the health of the process.

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Improving Yield Also Improves Device Reliability


The consequences of field failures (reliability defects) are much worse than those of non-functioning devices detected at electrical test (killer defects). Reliability defects result in angry customers, expensive failure analysis, the possibility of lost business, or worse.

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Know Your Enemy


Anything that degrades the quality of the measurement also degrades the quality of the process because it introduces more variability into the Statistical Process Control (SPC) charts which are windows into the health of the process.

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Fab Managers Don’t Like Surprises


Nobody likes surprises—especially the managers of $10 billion factories. In a dynamic field like advanced semiconductor IC fabrication, there will always be unknowns. However, it is critical to know what you know and know what you don’t know. Every measurement has error.

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Sampling Matters


Sampling is a unique concept to process control—you can’t sub-sample wafers to be etched, for example. The degree to which a factory will sample is based on the probability, projected from historical data, that an excursion will occur and the potential impact of that excursion.

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Exploring the Dark Side


When a 300mm wafer is vacuum mounted onto the chuck of a scanner, it needs to be flat to within about 16nm over a typical exposure field, for wafers intended for 28nm node devices. A particle as small as three microns in diameter, attached to the back side of the wafer – the dark side, if you will – can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer.

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Cycle Time’s Paradoxical Relationship to Inspection


In an IC fab, cycle time is the time interval between when a lot is started and when it is completed. The benefits of shorter cycle time during volume production are well known: reduced capital costs associated with having less work in progress (WIP); reduced number of finished goods required as safety stock; reduced number of wafers affected by engineering change notices (ECNs); reduced inventory costs in case of a drop in demand; more flexibility to accept orders, including short turnaround orders; and shorter response time to customer demands.

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A Clean, Well-Lighted Reticle


When something happens to a reticle, the consequences can be dire. Contamination in the wrong place on a reticle can result in a defect in every die of every wafer. Fabs have to keep their reticles clean. On the other hand, if the reticle is cleaned too many times, the pattern can start to erode. Reticle pattern degradation eventually causes critical dimension uniformity (CDU) changes on the wafer, which can translate into issues of device performance or yield.

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Yield Management Turns Green


As we celebrate Earth Day 2016, we commend the efforts of companies who have found ways to reduce their environmental impact. In the semiconductor industry, fabs have been building Leadership in Energy and Environmental Design (LEED)-certified buildings [1] as part of new fab construction and are working with suppliers to directly reduce the resources used in fabs on a daily basis.

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Risky Business


In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise.

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The Most Expensive Defect


Defect inspection tools can be expensive. But regardless of the cost of the inspection tool needed to find a defect, the fab is almost always better off financially if it can find and fix that defect inline versus at the end of line (e.g., electrical test and failure analysis).

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You Can't Fix What You Can't Find


If you can’t find it, you can’t fix it. At the heart of this truth is the understanding that, above all else, a fab’s inspection and metrology strategy must be capable. It must highlight the problems that are limiting baseline yield. And it must provide actionable information that can enable fabs to quickly find and fix excursions.

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The Gleam of Well-Polished Sapphire


Is it time for high-brightness LED manufacturing to get serious about process control? If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing? The answer to the first question can be approached in a straight-forward manner: by weighing the benefits of process control against the costs of the necessary equipment and labor.

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Breaking Parametric Correlation


When you’re designing a geometrically complex structure like a high-k metal gate, FinFET, or vertical DRAM, you will probably use SEM/TEM cross-sectional imaging to work out the bugs. Maybe even a touch of AFM. However, in production, optical scatterometry-based technology is used, chosen for its speed, non-destructive nature and ability to monitor the 3D shape of a feature. This group of metrology techniques is commonly called OCD (Optical Critical Dimension) or SCD (Scatterometry Critical Dimension).

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Taming the Overlay Beast


Overlay error is the offset in alignment between pattern at one step of a semiconductor process and pattern at the next step. Traditionally overlay error has referred to successive device layers, but in the case of double-patterning lithography, overlay error may stem from interwoven patterns at the same layer.

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Skewing the Defect Pareto


If you want to quickly find and fix the source of a process excursion, you have to be able to capture the right defects, and review and classify them efficiently.

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The Dangerous Disappearing Defect


Finding and classifying defects on a wafer is a statistics game. The defect pareto – the bar graph showing the number of defects by type caught by the defect inspector and identified by the e-beam review system – drives the actions of the defect engineers in the fab.

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Bigger and Better Wafers


Chip manufacturers need wafers that are both bigger and better: bigger to help achieve cost targets through gains in manufacturing efficiency, and better to help reach device performance targets through the time-honored path of the pattern shrink.

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