Spotlight: Lithography Users Forum - Keynote Address

Dr. Tatsuhiko Higashiki, Sr. Manager at Toshiba provides the keynote address at this year's Lithography Users Forum on Advanced Lithography.


Yield Enhancement of 3D Flash Devices through Broadband Brightfield Inspection of the Channel Hole Process Module

The migration to a 3D implementation for NAND flash devices is seen as the leading contender to replace traditional planar NAND architectures. The primary defect challenges for front end 3D NAND are buried particles, voids and bridges in the top, middle and bottom of high aspect ratio structures. Of particular interest are the yield challenges in the channel hole process module and developing an understanding of the contribution of litho and etch defectivity for this challenging new integration scheme. This study explores the use of broadband brightfield optical inspection for defect monitoring in the channel hole module.

  • Capturing Buried Defects in Metal Interconnections with Electron Beam Inspection System
  • DSA Hole Defectivity Analysis using Advanced Optical Inspection Tool
  • Defect Source Analysis of Directed Self-Assembly Process (DSA of DSA)

Overlay Accuracy Calibration

In order to fulfill the ever tightening requirements of advanced node overlay budgets, overlay metrology is becoming more sensitive to even the smallest imperfections in the metrology target. Under certain circumstances, inaccuracy due to such target imperfections can become the dominant contribution to the metrology uncertainty and cannot be quantified by the standard Total Measurement Uncertainty (TMU) contributors. In this paper we describe a calibration method that makes the overlay measurement robust to target imperfections without diminishing its sensitivity to the target overlay.

  • Quality Metric for Accurate Overlay Control in <20nm Nodes }
  • Advanced Gate CDU Control in Sub-28nm Node using Poly Slot Process by Scatterometry Metrology

Reflective Electron Beam Lithography: Lithography Results Using CMOS Controlled Digital Pattern Generator Chip

Reflective Electron Beam Lithography (REBL) uses a novel multi-column wafer writing system combined with an advanced stage architecture to enable the throughput and resolution required for a next-generation lithography system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Chip design improvements and the current chip performance on the REBL system are presented.

  • Optimization of a Virtual EUV Photoresist for the Trade-Off between Throughput and CDU
  • Preliminary Investigation of Shot Noise, Dose and Focus Latitude for e-Beam Direct Write