Winter Issue 2015

22 January, 2015


Addressing Thin Film Thickness Metrology Challenges of 14nm BEOL Layers

This paper describes a method to effectively monitor the film stack at different metal CMP process steps using a spectroscopic ellipsometer metrology tool. By proper modeling of the Cu dispersion and simulating the underlayer film information underneath the Cu pad, a single measurement recipe was developed which can be used to monitor each process step in the metal CMP process with stable and reliable results.




High-K Metal Gate Contact Process Optimization for Yield Improvement via Innovative Defect Inspection Technique

High-K metal gate processes induce new process and wafer defect inspection challenges compared with traditional poly silicon. Mechanisms of two systematic yield-limiting defects at the contact loop process step are discussed. In addition, an innovative method of defect detection and contact process improvement for 28nm high-K metal gate process ramping is shared. The new defect detection and process improvement method – utilizing e-beam, broadband plasma optical and laser scanning optical inspectors – has demonstrated faster time to results with >90% defect reduction and a SRAM yield gain of >20%.



In-Die Registration Measurement Using Novel Model-Based Approach for Advanced Technology Masks

In recent years, 193nm immersion lithography has been extended through multi-patterning technology, requiring tighter specification as the pattern size gets smaller on advanced semiconductor devices. In this environment, mask registration metrology faces challenges such as tight repeatability and complex in-die pattern measurement. In this study, the registration measurement capability was investigated on a new registration metrology tool. With the demonstrated evaluation results, it is highly expected that in-die measurements using the new registration metrology tool has the potential to help wafer fabs to improve wafer overlay.



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