SPOTLIGHT: 2011 Lithography Users’ Forum Keynote Presentation
Coinciding with the 2011 SPIE Advanced Lithography exhibition, KLA hosted its one-of-a-kind Lithography Users’ Forum (LUF). Annually, this event brings together the industry’s leading lithographers for networking, information sharing, and discussions surrounding challenges facing the industry and possible solutions.
The keynote address was given by Dr. Burn J. Lin, vice president of TSMC’s Nanopatterning Technology Division and editor-in-chief of the Journal of Micro/nanolithography, MEMS and MOEMS. Dr. Lin’s keynote, “Scope and Limit of Lithography to the End of Moore’s Law,” engaged a standing-room only audience of nearly 300 lithographers from around the world. Dr. Lin surmised that Moore’s Law will slow due to limitations related to devices, lithography, and the economy. Dr. Lin further examined the various ways in which the industry and technology is currently pushing the limits of Moore’s Law, including spacer-pitch splitting, Extreme Ultraviolet (EUV), and multiple e-beam maskless lithography, while also discussing how each of these approaches face unique challenges. His presentation illustrated the need for ongoing research to drive solutions at smaller nodes, while reinforcing KLA’s value in advancing process control at these advanced geometries.
Lithography Modeling
EUV Secondary Electron Blur at the 22nm Half Pitch Node
The impact of variation of post-exposure bake temperature on the blur components in a chemically amplified EUV resist has been studied quantitatively.
Additional Articles
- Stochastic Exposure Kinetics of EUV Photoresists: A Simulation Study
- Comprehensive EUV Lithography Model
- Physical Modeling of Developable BARC at KrF
- Characterization of a ‘Thermal Freeze’ Litho-Litho-Etch (LLE) Process for Predictive Simulation
- Stochastic Acid-Base Quenching in Chemically Amplified Photoresists: A Simulation Study
- Impact of Mask Line Roughness in EUV Lithography
- Negative Tone Development: Gaining Insight Through Physical Simulation
Overlay/CD Metrology
Scatterometry Measurement for Gate ADI and AEI Critical Dimension
Scatterometry-based metrology measurements of critical parameters on 28nm high k metal gate after-develop inspection and after-etch inspection layer structures are presented.
Additional Articles
- High-order Stitching Overlay Analysis for Advanced Process Control
- Methodology for Overlay Mark Selection
- Improved Overlay Control Using Robust Outlier Removal Methods
- Impact of Pellicle on Overlay in Double Patterning Lithography
- Metrology of Micro-Step Height Structures using 3D Scatterometry in 4xnm Advanced DRAM
- Simulation of Non-Uniform Wafer Geometry and Thin Film Residual Stress on Overlay Errors
Electron Beam Lithography
Demonstration of Lithography Patterns using Reflective E-beam Direct Write
The design, implementation and performance of a Reflective Electron Beam Lithography system is reviewed, including presentation of exposure tests done on device representative wafers.
