SPOTLIGHT: ASMC 2010
The 21st annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2010) was held July 11-13 at the San Francisco Marriott Marquis, in conjunction with this year’s SEMICON West and Intersolar North America conferences. The conference began with an interactive poster session and reception sponsored by KLA on Sunday, July 11. 21 papers were featured, authored by engineers from companies and universities from around the world. The rest of this year’s ASMC, held over July 12-13, consisted of 11 additional sessions presenting 49 technical papers, as well as three keynote speeches. The three keynotes, by Matt Nowak, Senior Director of Engineering, VLSI Technology Group, CDMA Technology Division, Qualcomm; Kalin Kuhn, Intel Fellow, Advanced Devices Technology, Intel Corporation; and Bill McClean, President, IC Insights. KLA partnered with IBM, GLOBALFOUNDRIES, imec and Timbre Technologies to present 10 technical papers at the conference.
Defect Inspection and Review
Voltage Contrast Test Structure for Measurement of Mask Misalignment
A new test structure for measuring mask misalignment for critical levels like contact to gate is described. Alignment requirements have become very challenging because of the extremely small dimensions of current state-of-the-art CMOS devices. The method for measuring contact to gate alignment involves using a SEM to scan an array of contacts each with a different amount of overlap with a grounded gate. The voltage contrast signal indicates which contacts are touching the gate. The data for an example wafer are compared to optical alignment data.
- Methodology for Trench Capacitor Etch Optimization using Voltage Contrast Inspection and Special Processing
- Process Window Centering for 22 nm Lithography
- Characterization of Contact Module Failure Mechanisms for SOI Technology using E-beam Inspection and In-line TEM
- Study of Relationship between 300 mm Si Wafer Surface and Annealing Temperatures for Advanced Semiconductor-Based Applications
Improved Scatterometry Time to Solution for Leading-Edge Logic Applications
This paper describes an innovative approach to scatterometry modeling, significantly reducing time to solution compared to the industry’s current best practices. One of the drawbacks to traditional scatterometry measurement techniques is the time required to optimize the model, which includes material optical constant extraction, model build time, initial model optimization, and model testing. A novel methodology that includes both stability and self-consistent scatterometry accuracy prediction can achieve an order of magnitude gain in productivity over prior methods.
In-Situ Process Monitoring
Study on Metrology of ERU Tuning in TCP Reactor Using PVx2 Sensor Wafer
Uniformity control in plasma etch processes and process stability requirements are major challenges in high-volume production and they are becoming more aggressive for each new node. Understanding the reason for possible drifts as well as facilitating on-line data acquisition are becoming key elements for effective process optimization. The effect of the transformer-coupled capacitive tuning (TCCT) parameter on the etch rate uniformity (ERU) in a high density plasma etch chamber was studied by the following means: blanket wafer experiments; tests on patterned wafers with 20-nm half-pitch BEOL interconnect trenches, created by spacer defined double patterning; and PlasmaVolt™ X2 sensor wafer experiments.
Papers first published in the Proceedings of the 21st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2010), 2010.