SPOTLIGHT: 2010 Lithography Users’ Forum
Over 300 technologists, scientists and engineers gathered in San Jose, California on February 21st to attend KLA’s 11th Annual Lithography Users’ Forum. This annual event serves as a sneak peek at more than 20 technical papers co-authored by KLA engineers and customers presented at SPIE’s Advanced Lithography conference. The forum covered current metrology and inspection challenges associated with today’s advanced lithography processes, and KLA’s solutions to those challenges. The event highlight was the keynote, “EUV, EBDW—ArF Replacement or Extension?” presented by Yan Borodovsky, director of the Advanced Lithography Technology, Manufacturing Group at Intel Corp.
After the keynote address, attendees had the opportunity to preview more than 20 technical papers. The manuscripts for many of the papers are included in this YMS issue.
Overlay/CD Metrology
Automated Optimized Overlay Sampling for High-Order Processing in Double Patterning Lithography
A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two significant inflections in the semiconductor industry require even more careful sampling consideration: the transition from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address the sampling challenges, an analysis tool in K-T Analyzer has been developed to enable quantitative evaluation of sampling schemes for both stage-grid and within-field analysis.
Additional Articles
- Use of Multiple Azimuthal Angles to Enable Advanced Scatterometry Applications
- Improved Scanner Matching Using Scanner Fleet Manager (SFM)
- Experimental Test Results of Pattern Placement Metrology on Photomasks with Laser Illumination Source Designed to Address Double Patterning Lithography Challenges
- Overlay Control Strategy for 45/32nm RD and Production Ramp Up
- Measurement Sampling Frequency Impact on Determining Magnitude of Pattern Placement Errors on Photomasks
- Mask Registration and Wafer Overlay
- In-depth Overlay Contribution Analysis of a Poly-layer Reticle
- Simultaneous Optimization of Dose and Focus Controls in Advanced ArF Immersion Scanners
EUVL Defect Inspection
The Analysis of EUV Mask Defects Using a Wafer Defect Inspection System
EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still critical challenges for EUVL to address to become a mature technology like today’s litho workhorse, ArF immersion. Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the requirement as of today. In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for detection of phase defects on the mask.
Additional Articles
Lithography Modeling
Methods for Benchmarking Photolithography Simulators: Part V
As the semiconductor industry moves to double patterning solutions for smaller feature sizes, photolithography simulators will be required to model the effects of non-planar film stacks in the lithography process. This presents new computational challenges for modeling the exposure, post- exposure bake (PEB), and development steps. The algorithms are more complex, sometimes requiring very different formulations than in the all-planar film stack case. It is important that the level of accuracy of the models be assessed. In this paper, we evaluate the accuracy of the new PROLITH wafer topography models.
Additional Articles
- Reflectivity Metrics for Optimization of Anti-reflection Coatings on Wafers with Topography
- Predictive Linewidth Roughness and CDU Simulation Using a Calibrated Physical Stochastic Resist Model
- Laser Spectrum Requirements For Tight CD Control At Advanced Logic Technology Nodes
- The Impact Of Resist Model On Mask 3D Simulation Accuracy Beyond 40nm Node Memory Patterns
- The Impact Of Optical Non-idealities In Litho-Litho-Etch Processing
- Inter-layer Self-Aligning Process for 22nm Logic
Litho Defect Inspection
Immersion and Dry Lithography Monitoring for Flash Memories (after develop inspection and photo cell monitor) Using a Darkfield Imaging Inspector with Advanced Binning Technology
After-develop inspection (ADI) and photo-cell monitoring (PM) are part of a comprehensive lithography process monitoring strategy. Capturing defects of interest (DOI) in the lithography cell rather than at later process steps shortens the cycle time and allows for wafer re-work, reducing overall cost and improving yield. Low contrast DOI and multiple noise sources make litho inspection challenging. Broadband brightfield inspectors provide the highest sensitivity to litho DOI and are traditionally used for ADI and PM. However, a darkfield imaging inspector has shown sufficient sensitivity to litho DOI, providing a high-throughput option for litho defect monitoring. This paper describes litho monitoring methodologies developed and implemented for flash devices for 65nm production and 45nm development using the darkfield imaging inspector.
Additional Articles
