ADVANCED PATTERNING CONTROL
Patterning Trends for Advanced IC Manufacturing
With the move to sub-10nm design nodes, the utilization of multi-patterning techniques has intensified, with triple patterning (LELELE), self-aligned quadruple patterning (SAQP), and other complex patterning technologies being utilized to achieve smaller design nodes. IC manufacturers face many technical challenges when implementing advanced multi-patterning, including: the proliferation of process and design systematic defects; extremely tight patterning specifications; and, the erosion of process margins. In this environment, it has become necessary for IC manufacturers to: (1) utilize comprehensive strategies to find and control process and patterning variations at the source.
ADDITIONAL ARTICLES
- Process Resilient Overlay Target Designs for Advanced Memory Manufacturer
- High-Volume Manufacturing Device Overlay Process Control
- Etch Process Monitoring Possibilities and Root Cause Analysis
- Patterned Wafer Geometry Grouping for Improved Overlay Control
- SAQP Pitch Walk Metrology Using Single Target Metrology
- Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned Wafers
- Manufacturing Excellence using Multi-Platform Ellipsometry Thickness Measurement Fleet on Advanced Nodes
- Modeling and Simulation of Low-Energy Electron Scattering in Organic and Inorganic EUV Photoresists
- A Novel Methodology for Litho-to-Etch Pattern Fidelity Correction for SADP Process
- Yield Enhancement in Stripper Process and Related Process using SensArray HighTemp Wafer
