The 21st annual IEEE/SEM Advanced Semiconductor Manufacturing Conference (ASMC 2010) was held July 11-13 at the San Francisco Marriott Marquis, in conjunction with this year’s SEMICON West and Intersolar North America conferences. The conference began with an interactive poster session and reception sponsored by KLA-Tencor on Sunday, July 11. 21 papers were featured, authored by engineers from companies and universities from around the world.
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PODCAST
Wafer-based useful correlation research from IMEC and KLA Tencor, Paul Arleo
Paul Arleo, Director of Applications Development, SensArray Division, KLA-Tencor, describes KLA-Tencor’s wafer-level wireless metrology.
The company is demonstrating wafers’ useful correlation in a TCP reactor, with results from IMEC. 20nm-pitch lithography has been produced in the work.
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FRONT END WAFER DEFECT INSPECTION AND REVIEW
Voltage Contrast Test Structure for Measurement of Mask Misalignment
A new test structure for measuring mask misalignment for critical levels like contact to gate is described. Alignment requirements have become very challenging because of the extremely small dimensions of current state-of-the-art CMOS devices. The method for measuring contact to gate alignment…
Methodology for Trench Capacitor Etch Optimization using Voltage Contrast Inspection and Special Processing
Embedded DRAM will play a much larger part in IBM server microprocessors for new SOI technologies. Etch of a deep trench (DT) into the substrate, which is used to form the capacitor, is a complicated multi-step process. One of the key elements is etch of the…
Process Window Centering (PWC) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that…
Characterization of Contact Module Failure Mechanisms for SOI Technology using E-beam Inspection and In-line TEM
Electron-beam inspection (eBI) of the contact (CA) module for silicon-on-insulator (SOI) technology is discussed in this paper. Voltage contrast is used to detect CA opens in the SRAM and both CA opens and shorts in special test structures. The inspection is performed after the tungsten chemical…
Study of Relationship between 300 mm Si Wafer Surface and Annealing Temperatures for Advanced Semiconductor-Based Applications
Surface morphology dependence on annealing conditions is one of the most important parameters that is being monitored in current manufacturing environments.
Improved Scatterometry Time to Solution for Leading-Edge Logic Applications
This paper describes an innovative approach to scatterometry modeling, significantly reducing time to solution compared to the industry’s current best practices.
Study on Metrology of ERU Tuning in TCP Reactor Using PVx2 Sensor Wafer
Uniformity control in plasma etch processes and process stability requirements are major challenges in high-volume production and they are becoming more aggressive for each new node.
